1. Technical Field of the Invention
The present invention relates to the field of semiconductor read-only memories (ROM). More specifically, it relates to a configurable array element for use in a read-only memory array and to a method of fabricating the array element.
2. Background Art
A ROM is a semiconductor device comprising an array of storage elements, or memory cells, and suitable addressing and sensing devices coupled thereto for determining the logic state of each storage element, or selected ones of the storage elements (selected by addressing or sensing means), when reading out data stored in the array. In one type of ROM array, diode elements are used as storage elements. One method of writing the information into the ROM is performed during fabrication of the ROM, sometimes termed mask programming. This type of ROM is capable of being fabricated with a high density of array elements. Typically, it is not possible to write to this type of memory after device fabrication is complete. Traditional uses of ROMs include storing BIOS or BASIC instructions in computers, character patterns for CRT display, or for storing security information.
Trends in semiconductor design are moving toward placing multiple circuit functions on the same die. The use of polysilicon diodes as ROM storage elements is attractive in a CMOS dual polysilicon gate technology because polysilicon diodes can be fabricated without additional process steps and without consuming crystalline silicon real estate.
Turning to the prior art, U.S. Pat. No. 4,516,223 to Erickson describes a lateral polysilicon diode used as a storage element in a mask programmed ROM array. FIG. 1 of the present application shows a schematic representation of the ROM device used in the prior art patent comprising bit lines 10, wordlines 12, and diode elements 14 connected to wordlines 12. Connecting circuit element 16 connects certain diodes to bit lines 10. The diodes are polysilicon and are coextensive with the wordlines, as will be described below. In this ROM device (FIG. 1) the programming of the ROM is done at the masking level used to define the vias, which vias act as the connecting elements 16 shown in FIG. 1. At least two additional levels of fabrication are required to complete the ROM device after this mask level programming step. For cost reasons it would be advantageous to delay this programming step until fabrication of the array is complete, thereby providing an inventory, or allowing stockpiling, of non-programmed devices until they are needed, and reducing part numbers, i.e. specially pre-programmed devices, in the manufacturing line.
The two logic states that must be sensed in this type of array are a diode junction or an open circuit. Using a CMOS inverter as a state sensor, the high state to be detected would be GND+V.sub.T and the low state V.sub.DD -V.sub.T giving a low-to-high signal margin defined as V.sub.DD -GND-2V.sub.T. Given a first case V.sub.DD =5v, GND=0v, and V.sub.T =0.7v the signal margin would be 3.6v. However as power supply voltages of modern semiconductor devices decrease, this signal margin will also decrease. Consider the second case: V.sub.DD =1.8v, GND=0v, and V.sub.T =0.5v where the signal margin would be 0.8v. Additionally, consider the third case V.sub.DD =1.3V, GND=0v, and V.sub.T =0.3v where the signal margin would be only 0.4v. Clearly, the trend of lower signal margins presents problems in detecting the logic state of arrays having diode junction and open logic states.
Therefore, there is a need in the industry for a ROM array formed of polysilicon diodes whose fabrication is compatible with CMOS device processing, possessing a high signal margin, and where programming of the ROM may optionally be delayed until post fabrication.